Hi, I’m Ayushman Malla — a hardware engineer and builder who enjoys thinking at the intersection of computing, design, and intelligence. I’m currently exploring how abstraction, verification, and synthesis shape the boundary between algorithms and silicon. My work often revolves around FPGA design, high-level synthesis (HLS), and digital verification, with a deep curiosity about how hardware can be reimagined for AI and high-performance systems.

Recently, I’ve been working at Transcelestial as an FPGA/Hardware Engineering Intern, developing a kind of packet forwader for 10G Ethernet. Beyond hardware, I’ve built some fun AI/ML Projects ranging from financial analytics tools to deep learning models for Medical Imaging and Autonomous Vehicles. I enjoy bridging low-level systems knowledge with modern ML models, understanding the full stack from transistor logic to inference runtime.

Outside of engineering, I find satisfaction in solving math puzzles((for some reason I am obssessed with Rubik's cubes), watching people cook and playing tennis! I value precision, iteration, and clarity of thought — qualities that guide how I approach both design problems and life in general.

I’m also fascinated by meta-cognition: how people structure knowledge, synthesize abstractions, and turn insight into execution. I usually try to focus on sharpening my reasoning frameworks.

This portfolio is a space where I share my projects, reflections, and ideas — from technical breakdowns to thought experiments. At its core, it’s a record of one ongoing pursuit: to build systems — and ways of thinking — that scale.